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71M6543F/71M6543G Data Sheet
Table 69 lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile
bits have a darker gray background.
Table 69: I/O RAM Map – Functional Order
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CE and ADC
MUX5 2100
MUX_DIV[3:0]
MUX10_SEL[3:0]
MUX4
MUX3
MUX2
MUX1
MUX0
2101
2102
2103
2104
2105
MUX9_SEL[3:0]
MUX7_SEL[3:0]
MUX5_SEL[3:0]
MUX3_SEL[3:0]
MUX1_SEL[3:0]
MUX8_SEL[3:0]
MUX6_SEL[3:0]
MUX4_SEL[3:0]
MUX2_SEL[3:0]
MUX0_SEL[3:0]
CE6
2106
EQU[2:0]
U
CHOP_E[1:0]
RTM_E
CE_E
CE5
CE4
CE3
CE2
CE1
2107
2108
2109
210A
210B
U
U
SUM_SAMPS[12:8]
SUM_SAMPS[7:0]
CE_LCTN[6:0] (71M6543G), CE_LCTN[5:0] (71M6543F)
PLS_MAXWIDTH[7:0]
PLS_INTERVAL[7:0]
CE0
RTM0
210C
210D
DIFF6_E
U
DIFF4_E
U
DIFF2_E
U
DIFF0_E
U
RFLY_DIS
U
FIR_LEN[1:0]
U
PLS_INV
RTM0[9:8]
RTM0
RTM1
RTM2
RTM3
210E
210F
2110
2111
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
CLOCK GENERATION
CKGN 2200
U
U
ADC_DIV
PLL_FAST
RESET
MPU_DIV[2:0]
VREF TRIM FUSES
TRIMT 2309
TRIMT[7:0]
LCD/DIO
LCD0
2400
LCD_E
LCD_MODE[2:0]
LCD_ALLCOM
LCD_Y
LCD_CLK[1:0]
LCD1
2401
LCD_VMODE[1:0]
LCD_BLNKMAP23[5:0]
LCD2
LCD_MAP6
LCD_MAP5
LCD_MAP4
LCD_MAP3
2402
2405
2406
2407
2408
LCD_BAT
R
LCD_BLNKMAP22[5:0]
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
98
v2
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